IC Design

Synopsys isthe world leader in electronic design automation (EDA), supplying the global electronics market with software, intellectual property (IP), systems and services used in semiconductor design and manufacturing.

The tool set used was

  • Synopsys VCS - Functional verification solution for 2 days
  • Synopsys DC - Synthesis solution for 2 days
  • Synopsys PT - Timing analysis solution for 1 day
  • Synopsys ICC - Physical implementation solution for 2 days
  • VCS (Verilog Compiler and Simulator) –

The primary objective of the training is getting familiar with complete custom IC (Application Specific ICs) design flow using Synopsys tool set, which is considered as industry standard. The sessions include introductory presentations and hands on lab sessions for each tools.

Topics covered were,

  1. VCS flow
  2. Common compile/run time switches
  3. Gate level simulations
  4. Dumping and Waveform debugging
  5. Code coverage
  6. Functional Coverage
  7. Introduction to Assertions
  • DC (Design Compiler) –
  1. Introduction to High Level Design
  2. Introduction to Synthesis
  3. Design and Technology Data
  4. Design and Library Objects
  5. Timing Constraints
  6. Synthesis Optimization Techniques
  7. Timing Analysis
  8. Post-Synthesis Output Data
  • PT (Prime Time) –
  1. Timing Violations and ECO
  2. Clock constraints
  3. Additional checks and constraints
  • ICC (IC compiler - Place and Route) –
  1. Design Setup and Basic Flow
  2. Design Planning
  3. Placement
  4. Clock Tree Synthesis
  5. Routing
  6. Design for Manufacturability

The training is targeted towards ASIC digital designers with adequate theoretical background but with little or no tool experience. 

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